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cy7c1049d 4-mbit (512 k 8) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05474 rev. *e revised april 20, 2011 features pin- and function-compatible with cy7c1049b high speed ? t aa = 10 ns low active power ? i cc = 90 ma at 10 ns low cmos standby power ? i sb2 = 10 ma 2.0 v data retention automatic power-down when deselected ttl-compatible inputs and outputs easy memory expansion with ce and oe features available in pb-free 36-pin (400-mil) molded soj package functional description [1] the cy7c1049d is a high-performance cmos static ram organized as 512k words by 8 bits. easy memory expansion is provided by an active low chip enable (ce ), an active low output enable (oe ), and tri-state drivers. writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. data on the eight i/o pins (i/o 0 through i/o 7 ) is then written into the location specified on the address pins (a 0 through a 18 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing write enable (we ) high. under these conditions, the contents of the memory location specified by the address pins will appear on the i/o pins. the eight input/output pins (i/o 0 through i/o 7 ) are placed in a high-impedance state when the device is deselected (ce high), the outputs are disabled (oe high), or during a write operation (ce low, and we low). the cy7c1049d is available in a standard 400-mil-wide 36-pin soj package with cent er power and ground (revolu- tionary) pinout. note 1. for guidelines on sram system design, refer to the ?system design guidelines? cypress application note, available on the inte rnet at www.cypress.com . 14 15 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps input buffer power down we oe i/o 0 i/o 1 i/o 2 i/o 3 512k x 8 i/o 7 i/o 6 i/o 5 i/o 4 a 0 a 11 a 13 a 12 a ce a a 16 a 17 a 9 a 18 a 10 logic block diagram selection guide ?10 unit maximum access time 10 ns maximum operating current 90 ma maximum cmos standby current 10 ma [+] feedback
cy7c1049d document #: 38-05474 rev. *e page 2 of 12 contents pin configuration ............................................................. 3 maximum ratings ............................................................. 3 operating range ............................................................... 3 electrical characteristics over the operating range ............................................... 3 capacitance ...................................................................... 4 thermal resistance .......................................................... 4 ac test loads and waveforms ....................................... 4 switching characteristics over the operating range ............................................... 5 data retention characteristics over the operating range ............................................... 5 data retention waveform ................................................ 6 switching waveforms ...................................................... 6 truth table ........................................................................ 9 ordering information ........................................................ 9 ordering code definitions ..... ...................................... 9 package diagram ............................................................ 10 acronyms ........................................................................ 10 document conventions ................................................. 10 units of measure ....................................................... 10 document history page ................................................. 11 sales, solutions, and legal information ...................... 12 worldwide sales and design s upport ......... .............. 12 products .................................................................... 12 psoc solutions ......................................................... 12 [+] feedback
cy7c1049d document #: 38-05474 rev. *e page 3 of 12 pin configuration maximum ratings exceeding maximum ratings may s horten the useful life of the device. user guidelines are not tested. storage temperature ................................. ?65 c to +150 c ambient temperature with power applied ............................................ ?55 c to +125 c supply voltage on v cc to relative gnd [2] ...?0.5 v to +6.0 v dc voltage applied to outputs in high z state [2] .................................. ?0.5 v to v cc + 0.5 v dc input voltage [2] .............................. ?0.5 v to v cc + 0.5 v current into outputs (low)..... .................................... 20 ma static discharge voltage........................................... >2001 v (per mil-std-883, method 3015) latch-up current ..................................................... >200 ma 1 2 3 4 5 6 7 8 9 10 11 14 23 24 28 27 26 25 29 32 31 30 top view soj 12 13 33 36 35 34 16 15 21 22 gnd a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 we v cc a 18 a 15 a 12 a 14 i/o 5 i/o 4 a 9 a 0 i/o 0 i/o 1 i/o 2 oe a 17 a 16 a 13 ce 18 17 19 20 gnd i/o 7 i/o3 i/o 6 v cc a 10 a 11 nc nc operating range range ambient temperature v cc industrial ?40 c to +85 c 4.5 v?5.5 v electrical characteristics over the operating range parameter description test conditions ?10 min. max. unit v oh output high voltage v cc = min., i oh = ?4.0 ma 2.4 ? v v ol output low voltage v cc = min., i ol = 8.0 ma ? 0.4 v v ih [2] input high voltage 2.0 v cc + 0.5 v v il [2] input low voltage [2] ?0.5 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 a i oz output leakage current gnd < v out < v cc , output disabled ?1 +1 a i cc vcc operating supply current v cc = max., f = f max = 1/t rc 100 mhz ? 90 ma ? 83 mhz ? 80 ma ? 66 mhz ? 70 ma ? 40 mhz ? 60 ma ? i sb1 automatic ce power-down current ?ttl inputs max. v cc , ce > v ih , v in > v ih or v in < v il , f = f max ?20ma i sb2 automatic ce power-down current ?cmos inputs max. v cc , ce > v cc ? 0.3 v, v in > v cc ? 0.3 v, or v in < 0.3 v, f = 0 ?10ma [+] feedback
cy7c1049d document #: 38-05474 rev. *e page 4 of 12 capacitance [3] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0 v 8pf c out i/o capacitance 8 pf thermal resistance [3] parameter description test conditions soj package unit ja thermal resistance (junction to ambient) [3] still air, soldered on a 3 4.5 inch, four-layer printed circuit board 57.91 c/w jc thermal resistance (junction to case) [3] 36.73 c/w ac test loads and waveforms [4] 90% 10% 3.0 v gnd 90% 10% all input pulses 5 v output 5 pf including jig and scope (c) 3 ns 3 ns output r1 481 r2 255 167 equivalent to: venin equivalent 1.73 v th * capacitive load consists of all components of the test environment 30 pf* output z = 50 50 1.5 v (a) 10-ns device high-z characteristics (b) notes 2. minimum voltage is ?2.0 v and v ih (max) = v cc + 2 v for pulse durations of less than 20 ns. 3. tested initially and after any design or proces s changes that may affect these parameters. [+] feedback
cy7c1049d document #: 38-05474 rev. *e page 5 of 12 switching characteristics [5] over the operating range -10 parameter description min. max. unit read cycle t power v cc (typical) to the first access [6] 100 ? s t rc read cycle time 10 ? ns t aa address to data valid ? 10 ns t oha data hold from address change 3 ? ns t ace ce low to data valid ? 10 ns t doe oe low to data valid ? 5 ns t lzoe oe low to low z [8] 0?ns t hzoe oe high to high z [7, 8] ?5ns t lzce ce low to low z [8] 3?ns t hzce ce high to high z [7, 8] ?5ns t pu ce low to power-up 0 ? ns t pd ce high to power-down ? 10 ns write cycle [9, 10] t wc write cycle time 10 ? ns t sce ce low to write end 7 ? ns t aw address set-up to write end 7 ? ns t ha address hold from write end 0 ? ns t sa address set-up to write start 0 ? ns t pwe we pulse width 7 ? ns t sd data set-up to write end 6 ? ns t hd data hold from write end 0 ? ns t lzwe we high to low z [8] 3?ns t hzwe we low to high z [7, 8] ?5ns data retention characteristics over the operating range parameter description conditions [12] min. max unit v dr v cc for data retention 2.0 ? v i ccdr data retention current v cc = v dr = 2.0 v, ce > v cc ? 0.3 v v in > v cc ? 0.3 v or v in < 0.3 v ?10ma t cdr [3] chip deselect to data retention time 0 ? ns t r [11] operation recovery time t rc ?ns notes 4. ac characteristics (except high-z) for 10-ns parts are tested using the load conditions shown in figure (a). high-z character istics are tested for all speeds using the test load shown in figure (c) 5. test conditions assume signal transition ti me of 3 ns or less, timing reference levels of 1.5 v, input pulse levels of 0 to 3 .0 v, and output loading of the specified i ol /i oh and 30-pf load capacitance. 6. t power gives the minimum amount of time that the power supply should be at typical v cc values until the first memory access can be performed. 7. t hzoe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (c) of ac test loads. transition is measured when the outputs enter a high impedance state. 8. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 9. the internal write time of the memory is defined by the overlap of ce low, and we low. ce and we must be low to initiate a write, and the transition of either of these signals can terminate the write. the input data set-up and hold timing should be referenced to the leading edge of the signal that term inates the write. 10. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd . [+] feedback
cy7c1049d document #: 38-05474 rev. *e page 6 of 12 data retention waveform switching waveforms figure 1. read cycle no. 1 [13, 14] 4.5 v 4.5 v t cdr v dr > 2 v data retention mode t r ce v cc previous data valid data valid t rc t aa t oha address data out notes 11. full device operation requires linear v cc ramp from v dr to v cc(min.) > 50 s or stable at v cc(min.) > 50 s 12. no input may exceed v cc + 0.5 v. 13. device is continuously selected. oe , ce = v il . 14. we is high for read cycle. [+] feedback
cy7c1049d document #: 38-05474 rev. *e page 7 of 12 figure 2. read cycle no. 2 (oe controlled) [14, 15] figure 3. write cycle no. 1 (ce controlled) [16, 17] switching waveforms (continued) 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd high oe ce i cc i sb impedance address data out v cc supply current t wc data valid t aw t sa t pwe t ha t hd t sd t sce t sce ce address we data i/o notes 15. address valid prior to or coincident with ce transition low. 16. data i/o is high impedance if oe = v ih . 17. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. [+] feedback
cy7c1049d document #: 38-05474 rev. *e page 8 of 12 figure 4. write cycle no. 2 (we controlled, oe high during write) [16, 17] figure 5. write cycle no. 3 (we controlled, oe low) [17] switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe data in valid ce address we data i/o oe note 18 data valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce address we data i/o note 18 [+] feedback
cy7c1049d document #: 38-05474 rev. *e page 9 of 12 m bngggggggg truth table ce oe we i/o 0 ?i/o 7 mode power h x x high-z power-down standby (i sb ) l l h data out read active (i cc ) l x l data in write active (i cc ) l h h high-z selected, outputs disabled active (i cc ) ordering information speed (ns) ordering code package diagram package type operating range 10 CY7C1049D-10VXI 51-85090 36-lead (400-mil) molded soj (pb-free) industrial ordering code definitions please contact your local cypress sales repr esentative for availability of these parts. temperature range: i = industrial package type: vx = 36-lead molded soj (pb-free) speed: 10 ns d = c9, 90 nm technology 9 = data width 8-bits 04 = 4-mbit density 1 = fast asynchronous sram family technology code: c = cmos 7 = sram cy = cypress c cy 1 - 10 vx 7 04 d i 9 note 18. during this period the i/os are in the output state and input signals should not be applied. [+] feedback
cy7c1049d document #: 38-05474 rev. *e page 10 of 12 acronyms document conventions units of measure package diagram figure 6. 36-pin (400-mil) molded soj (51-85090) 51-85090 *e acronym description ce chip enable cmos complementary metal oxide semiconductor i/o input/output oe output enable sram static random access memory soj small outline j-lead tsop thin small outline package vfbga very fine-pitch ball grid array symbol unit of measure ns nano seconds vvolts a micro amperes ma milli amperes mv milli volts mw milli watts mhz mega hertz pf pico farad c degree celcius wwatts [+] feedback
cy7c1049d document #: 38-05474 rev. *e page 11 of 12 document history page document title: cy7c1049d 4-mbit (512k x 8) static ram document number: 38-05474 revision ecn orig. of change submission date description of change ** 201560 swi see ecn advance datasheet for c9 ipp *a 233729 rkf see ecn 1.ac, dc parameters are modified as per eros(spec # 01-2165) 2.pb-free offering in the ?ordering information? *b 351096 pci see ecn changed from advance to preliminary removed 17, 20 ns speed bin added footnote # 4 redefined i cc values for com?l and ind?l temperature ranges i cc (com?l): changed from 67 and 54 ma to 75 and 70 ma for 12 and 15 ns speed bins respectively i cc (ind?l): changed from 80, 67 and 54 ma to 90, 85 and 80 ma for 10, 12 and 15 ns speed bins respectively added v ih(max ) spec in note# 2 modified note# 10 on t r changed t sce from 8 to 7 ns for 10 ns speed bin changed reference voltage level for measurement of hi-z parameters from 500 mv to 200 mv added truth table on page# 6 removed l-version added 10 ns parts in the ordering information table added lead-free product information shaded ordering information table *c 446328 nxr see ecn converted from preliminary to final removed -12 and -15 speed bins removed commercial operating range product information changed maximum rating for supply voltage from 7 v to 6 v updated thermal resistance table changed t hzwe from 6 ns to 5 ns updated footnote #7 on high-z parameter measurement replaced package name column with package diagram in the ordering infor- mation table *d 3109184 aju 12/13/2010 added ordering code definitions . updated package diagram . *e 3235742 pras 04/20/2011 updated template. added acronyms and units of measure. [+] feedback
document #: 38-05474 rev. *e revised april 20, 2011 page 12 of 12 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c1049d ? cypress semiconductor corporation, 2004-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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